1. Field of the Invention
This invention relates generally to integrated circuits and, in particular, to a method and apparatus for global testing the impedance of a programmable element within a memory circuit.
2. Description of the Related Art
Typical memory circuits include arrays of memory cells arranged in rows and columns. These memory circuits will also include several redundant rows and columns that are used as substitutes for defective locations in the memory array. When a defective memory array location is identified, rather than treating the entire array as defective, a redundant row or column is substituted for the defective row or column. This substitution is performed by assigning the address of the defective row or column to the redundant row or column such that, when an address signal corresponding to the defective row or column is received, the redundant row or column is addressed instead.
To make the substitution of the redundant row or column substantially transparent to a system including the memory circuit, the memory circuit utilizes an address detection circuit. The address detection circuit monitors row and column addresses and enables redundant rows or columns if the address of a defective row or column is detected. FIG. 1 illustrates the typical memory circuit 10 including an address detection circuit 100, control and address circuitry 12, an array of memory cells 14 and row and columns of redundant memory cells 16.
One type of address detection circuit 100 is a fuse-bank address detection circuit. A fuse-bank address detection circuit utilizes several fuse-bank circuits to control the redundant rows and columns. Each fuse-bank circuit corresponds to one of the redundant rows or columns. If there are eight redundant rows and eight redundant columns, for example, then the address detection circuit 100 will include sixteen fuse-bank circuits. Each fuse-bank circuit includes a bank of sense lines, each sense line connected to a respective fuse. Each sense line corresponds to one bit of a memory address since each fuse-bank will be programmed with an address of a defective memory array location. If an address comprises eight bits, then each fuse-bank circuit includes eight sense lines, each with corresponding fuses.
The sense lines are "programmed" by blowing fuses in a pattern corresponding to the address word of the defective row or column (hereinafter referred to as the programmed addresses). The programmed addresses are then detected by initially applying a test voltage across the bank of sense lines. Then, bits of an external address are applied to the sense lines. If the pattern of blown fuses corresponds exactly to the pattern of the external address bits, the sense lines block current and the voltage across the bank remains latched high. Otherwise, at least one sense line conducts and the voltage falls. Therefore, a high voltage indicates that the programmed address matches the external address while a low address does not. A matched address indicates that the redundant row or column should be used.
Recently, to save the costs and labor required to blow the conventional fuse, antifuses have replaced fuses in the address detection circuit 100. Antifuses are capacitive-type structures which, in their unblown states, form open circuits. Antifuses are "blown" by applying a high voltage across the antifuse. The high voltage causes the capacitive-type structure to break down, forming a conductive path through the antifuse. Therefore, blown antifuses conduct while unblown anitifuses do not.
FIG. 2a illustrates an antifuse circuit 110 used in an antifuse-bank circuit. The circuit 110 corresponds to one bit of a programmed address. As previously stated, if an address consisted of eight bits, then each antifuse-bank circuit would include eight antifuse circuits 110. An antifuse 112, illustrated in its unblown state, is connected to a switchable signal CGND and a latch circuit 114. During normal operation, the switchable signal CGND is a ground potential to provide a reference for the antifuse 112. To blow or "program" the antifuse 112, the switchable signal CGND is supplied with a high voltage sufficient enough to cause the capacitive-type structure of the antifuse 112 to break down. Generally, the high voltage used to blow the antifuse is referred to as a programming voltage. Once blown, the antifuse 112 has a known impedance, plus or minus a predetermined margin, which is detected by the latch circuit 114. FIG. 2b illustrates the antifuse circuit 110 of FIG. 2a where the blown antifuse 112 is represented by its known impedance R.sub.112. When strobed by logic in the address detection circuit 100, the latch circuit 114 detects the impedance R.sub.112 of the antifuse 112 and outputs an output signal that is either a logical "1" if the antifuse is blown or a logical "0" if the antifuse is not blown. This output signal when combined with the output signals of the remaining antifuse circuits 110 of the antifuse-bank circuit forms an address of a defective memory location (i.e., a programmed address). The operation of antifuse in an address detection circuit 100 is described, for example, in U.S. Pat. No. 5,374,617 (Zheng), U.S. Pat. No. 5,742,555 (Marr et al.), and U.S. Pat. No. 5,706,238 (Cutter et al.), all assigned to Micron Technology Inc. and incorporated by reference herein.
One known problem with antifuses 112 is that they may not always have their expected or desired impedance R.sub.112 after being programmed. As stated above, an external address is received by the address detection circuit 100 which is compared to the antifuse-bank programmed addresses. The anitfuses 112 of each antifuse-bank, corresponding to an address of a defective row or column, must be read and latched by the latch circuits 114 and then compared to the external address. There must be an exact match before a redundant row or column can be used. If the impedance R.sub.112 of the antifuse 112 is not low enough, the latch circuit 114 will not detect that the antifuse 112 is blown and therefore, the correct status (i.e., blown antifuse 112) of the antifuse 112 will not be latched; this leads to a programmed address that does not match the defective address. Since the external address does not match any of the programmed addresses, the address detection circuit 100 will not substitute a redundant row or column for a defective row or column. In fact, the programmed address may match an external address of a non-defective memory array location. Accordingly, the redundant memory may substitute for good memory.
FIG. 3 illustrates a mechanism of testing the impedances R.sub.112 of antifuses 112. Four antifuse circuits 110 are illustrated, each having a respective antifuse 112 and associated latch 114. It must be noted, however, that there would be an antifuse circuit 110 for every bit in a programmed address and that four circuits 110 are illustrated for convenience purposes only. A test circuit for testing the impedance value of the antifuse 112 is also shown as test latch circuit 106 and multiplexer 104. The outputs of the circuits 110 are connected to a multiplexer 104. The multiplexer 104 is connected to a test latch circuit 106. The test latch circuit 106 is configured in the same manner as the latch circuits 114 included in the antifuse circuits 110. That is, the test latch circuit 106 will detect whether an antifuse 112 has been blown by measuring its impedance R.sub.112.
When testing the impedances of the antifuses 112, the multiplexer 104 sequentially connects the antifuses 112 to the test latch circuit 106. The test latch circuit 106 compares the impedance R.sub.112 of the antifuse 112 being tested to a reference impedance R.sub.REF (i.e., the expected impedance plus a margin). If the impedance R.sub.112 is greater than the reference impedance R.sub.REF and the antifuse 112 has been blown, then the antifuse 112 impedance R.sub.112 would lead to an erroneous programmed address when sensed by the latch circuit 114. Repairs or replacements would be required in order to use the antifuse circuit 110. If the impedance R.sub.112 is less than the reference impedance R.sub.REF, then the antifuse 112 would not lead to an erroneous programmed address and the antifuse circuit 110 will be used. Each antifuse circuit 110 is tested one at a time by the test latch circuit 106 during sequential operation of the multiplexer 104.
Although the above mechanism can properly detect when a blown antifuse 112 has an impedance R.sub.112 that is too high and would lead to incorrect programmed addresses, it still has some shortcomings. For example, the mechanism illustrated in FIG. 3 requires the use of a multilplexer 104 and a test latch circuit 106 and the numerous respective connections to the antifuse circuits 110. This additional circuitry adds costs and uses up valuable space on the semiconductor die. In addition, the antifuses 112 are tested one at a time in a sequential manner. This leads to slower testing of the antifuses 112, particularly if numerous redundant rows and columns were to be used.
Therefore, there is a need and desire to provide a method and apparatus for global testing the impedance of an antifuse while reducing the circuitry required to perform the testing.
In addition, manufacturers may require a blown antifuse 112 to have a smaller impedance margin during in-house testing than is actually required by users once the product is out in the field. To do so, however, a test latch circuit 106 that is not configured the same as the latch circuits 114 would be required. This adds additional steps in the manufacturing process of the memory circuit 10 and again consumes more circuit area. Therefore, there is a need and desire to provide a method and apparatus for testing the antifuse for different impedance values, but without requiring test circuitry that differs from the circuitry required to latch the status of the antifuse.